Current limiting using PWM control

ABSTRACT

A method and a system for current limiting using PWM control have been provided. The method includes sensing a load current to produce a control voltage. The control voltage is compared with a reference voltage to produce a detected output signal. Thereafter, the detected output signal is delayed and multiplied with a master PWM signal.

BACKGROUND OF THE INVENTION

Controlled voltage power supply circuits can commonly be regulated but,regulation arrangements in variable power supply circuits are typicallynot able to provide adequate protection against over-current or shortcircuit conditions. One such circuit protection problem relates to fanstart-up conditions that impact variable power supply requirements. Thecurrent drawn by fans at their start-up can be much greater than thenormal current drawn for operating. Moreover, for those types of fansthat are hot-swappable or are connected with cables, protection for asituation of over-current is required for both safety as well asequipment protection reasons.

FIELD OF THE INVENTION

The present invention relates, in general, to limiting current inelectronic devices and more specifically to current limiting inelectronic devices, such as DC motors used with fans, by using PulseWidth Modulation (PWM) techniques.

DESCRIPTION OF THE RELATED ART

To protect against over-current and short circuit, one technique usescircuit breakers and fuses. But circuit breakers are relativelyexpensive and fuses are difficult to replace once the over-currentconditions are cleared. Moreover, fuses and circuit breakers must beselected to allow for the normal inrush current associated with startingfans which requires designing circuits for larger, current capability.If fuses or circuit breakers are not sized for this inrush current, thenthey must be slow-blow type devices that slowly respond in anover-current condition.

Another technique for protection against over-current and short circuitis to use a Pulse Width Modulation (PWM) control circuit for powersupply. A primary PWM control circuit works by making a square wave witha variable on-time to off-time ratio, the on-time may be varied from 0to 100 percent. In this manner, a variable amount of power istransferred to the load. But the primary PWM control circuit may operatein an open loop or control power based on factors other than loadcurrent.

In view of the foregoing discussion, there is a need for a techniquethat can regulate overload and short circuit without operatorintervention once the load returns to a normal situation. Moreover, sucha system is required that can respond instantaneously to inrush currenton the start-up of a fan. Furthermore, a system is required that allowscontrol of fan current to be independent of all the factors other thanload current. The present invention addresses such needs.

SUMMARY OF THE INVENTION

The present invention relates to limiting current in electronic devices,such as electric motors. Specifically, the present invention relates tolimiting current using PWM control.

An object of the present invention is to provide a system and a methodfor current limiting using a PWM signal independent of a master PWMsignal. Moreover, the PWM signal is independent of all the factors otherthan a load current.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the mariner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference tovarious embodiments, some of which are illustrated in the appendeddrawings. It is to be noted, however, that the appended drawingsillustrate only typical embodiments of this invention and are thereforenot to be considered limiting of its scope, for the invention may admitto other equally effective embodiments.

FIG. 1 is a view of a system for current limiting using PWM control, inaccordance with an embodiment of the present invention;

FIG. 2 is a view of a flowchart illustrating a method for currentlimiting using PWM control, in accordance with an embodiment of thepresent invention;

FIG. 3 is a view showing an unfiltered detector output and a filtereddetector output, in accordance with an embodiment of the presentinvention; and

FIG. 4 is a view showing a circuit diagram for current limiting usingPWM control is shown, in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not limited tothese embodiments only. Numerous modifications, changes, variations,substitutions and equivalents will be apparent to those skilled in theart without departing from the spirit and scope of the invention asdescribed in the claims.

An embodiment of the present invention relates to a system and a methodfor current limiting using Pulse Width Modulation (PWM). Anotherembodiment of the present invention relates to the controlling of thecurrent to a fan independent of the master PWM signal. More generally,the embodiments of the invention are applicable to any DC motor orDC-to-DC power supply.

FIG. 1 is a view of a system 100 that limits current using PWM control,in accordance with an embodiment of the present invention. System 100comprises a current sensing circuit 102, an over-current comparatorcircuit 104, a low-pass filter 106, and a one-bit multiplier 108.Current sensing circuit 102 measures a load current and produces acontrol voltage proportional to the load current. In an embodiment ofthe present invention, current sensing circuit 102 comprises acombination of resistors in a series with a load. In another embodimentof the present invention, current sensing circuit 102 comprises anoperational amplifier. Further, the operational amplifier has afrequency response greater than a master PWM signal. The master PWMsignal can be generated by a PWM generator. PWM generators are wellknown in art, and are readily commercially available from multiplesuppliers. The selection of a suitable PWM generator is within the skillof the art, and does not comprise an element of this invention. Themaster PWM signal controls the final output based on factors other thanthe load current. Further, over-current comparator circuit 104 comparesthe control voltage with a reference voltage. The reference voltage isproportional to the specified maximum current limit of system 100. Themaximum current limit is specified based on the circuit components ofsystem 100. Over-current comparator circuit 104 generates a detectedoutput based on the reference voltage and the control voltage. If thecontrol voltage is greater than the reference voltage, the detectedoutput is set to logic zero. If the control voltage is less than thereference voltage, the detected output is set to logic one. The detectedoutput of comparator circuit 104 and the master PWM signal can have thesame or different frequencies.

In an embodiment of the present invention, over-current comparatorcircuit 104 can be an amplifier, such as an LM393/SO, commerciallyavailable from a variety of vendors. Further, low-pass filter 106 delaysthe detected output. Low-pass filter 106 delays the detected output bythe filter off-time during transition of the detected output from logiczero to logic one. The details of the delaying function are explained inconjunction with FIG. 3. In an embodiment of the invention, one-bitmultiplier 108 multiplies the delayed detected output with a master PWMsignal. One-bit multiplier 108 produces a PWM output signal that haspower consistent with the lower of the delayed detected output and themaster PWM signal. That is, if the delayed detected output or master PWMsignal is logic zero then the PWM output is zero. In an embodiment ofthe invention, if the delayed detected output is logic one, then the PWMoutput is equivalent to the master PWM signal.

FIG. 2 is a view of a flowchart of a method for limiting current usingPWM control, in accordance with an embodiment of the present invention.At step 202, a load current is sensed and a control voltage proportionalto the load current is produced. In an embodiment of the presentinvention, the load current is sensed by current sensing circuit 102. Inanother embodiment of the present invention, an operational amplifiermay be used for scaling the control voltage proportional to the loadcurrent.

At step 204, the control voltage is compared with a reference voltage.The reference voltage is proportional to maximum current limit of thesystem to be regulated. In an embodiment of the present invention, theappropriate reference voltage can be generated using a DC power sourcein combination with one or more resistors. In an embodiment of thepresent invention, the control voltage is compared with the referencevoltage by over-current comparator circuit 104. When the control voltageis greater than the reference voltage, the detected output is set tologic zero, else the detected output is set to logic one. The details ofswitching of the detected output are explained in conjunction with FIG.3.

At step 206, the detected output is delayed. In an embodiment of thepresent invention, the detected output is delayed by low-pass filter106, which delays the detected output by the filter off-time duringtransition of the detected output from logic zero to logic one. The lowpass filter further serves to decrease the frequency of the detectedoutput. The reduction in the frequency is necessary to avoid interactionwith the components used for reducing electromagnetic interference in aswitching power supply. The output of low-pass filter 106 is hereinafterreferred to as a delayed detected output. At step 208, the delayeddetected output is multiplied with a master PWM signal. In an embodimentof the invention, the delayed detected output is multiplied bit-by-bitwith the master PWM signal by one-bit multiplier 108 to yield a productPWM signal. The product PWM signal has power consistent with the lowerof the delayed detected output and the master PWM signal. That is, ifthe delayed detected output or master PWM signal is logic zero, then thePWM output is zero.

FIG. 3 is a view showing an unfiltered detector output and a filtereddetector output, in accordance with an embodiment of the presentinvention. The unfiltered detector output herein referred is same as thedetected output of the over-current comparator circuit 104, explained inconjunction with FIG. 2. The filtered detector output herein referred issame as the delayed detected output from low pass filter 106, alsoexplained in conjunction with FIG. 2. In an embodiment of the presentinvention, the current limit is the maximum allowed current for system100. The reference voltage is proportional to the current limit.

The logic output from current comparator 104 is the solid line labeledas the detected output in FIG. 3, the logic output being either high (aone), or low (a zero). In an embodiment of the present invention, whenthe load current is more than the current limit, over-current comparatorcircuit 104 switches the detected output to logic zero. Detector on-timeis the inherent delay of over-current comparator circuit 104 whileswitching its output from logic one to logic zero. Similarly, when theload current is less than the current limit over-current comparatorcircuit 104 switches the detected output to logic one. Detector off-timeis the inherent delay of over-current comparator circuit 104 whileswitching the detected output from logic zero to logic one. Further,system off-time and the system on-time, as shown in the FIG. 3,represent the response times of the remainder of the circuit, such asthe one illustrated in FIG. 4, which includes one-bit multiplier 108 andthe switching power supply, elements Q3, L3, D2 and C4, to changes inoutput from over-current comparator circuit 104.

In an embodiment of the present invention, low-pass filter 106 delaysthe detected output to produce the delayed detected output. A filteroff-time is the time delay introduced in the detected output by low-passfilter 106. The delay in the detected output is introduced only whileswitching the detected output from logic zero to logic one. In anembodiment of the present invention, the delay comprises extending thelogic zero state of the detected output.

FIG. 4 illustrates a circuit diagram for current limiting using PWMcontrol, in accordance with an embodiment of the present invention. Itis to be appreciated that the circuit of this figure is provided by wayof illustration only, in order to give an example of various circuitcomponents that may be used to construct the various functional circuitsof the invention. Other off the shelf components may be used in place ofthose depicted in the drawing, with different values, the selection ofsuch other components within the skill of the art, and not a part ofthis invention. It should be further understood that the valuesdiscussed in connection with the various components are provided forillustrative purposes only, and are intended to be exemplary, and notlimiting of the invention.

In an embodiment of the present invention, port GNDOUT1 receives a loadcurrent; current sensing element R2 converts the load current to acontrol voltage. The control voltage is provided at port 2 of voltagecomparator VCMP. In an embodiment of the invention, the comparator canbe an LM393/SO voltage comparator. A reference voltage is provided atport 3 of comparator VCMP. The reference voltage is proportional to acurrent limit of system 100. In an exemplary embodiment of the presentinvention, the reference voltage is 100 millivolts (mV) and the currentlimit is 2.13 ampere (A). Comparator VCMP produces a detected output atits port 1. The detected output is logic zero if the control voltage ismore than the reference voltage. Otherwise, the detected output is logicone.

In an embodiment of the present invention, diode D1 can be a BAT54Schottky diode. Further, logic zero at port 1 of Comparator VCMP forwardbiases diode D1. Forward biasing of diode D1 produces logic zero at thegate of transistor Q1B. In an embodiment of the present invention,transistors Q1B and Q1A can be the same, such as an NDC7002N fieldeffect transistor. Further, logic zero at the gate of transistor Q1Bdrives transistor Q1B into a cut-off region thus pushing port 4 oftransistor Q1B to a high impedance state. The high impedance state ofport 4 of transistor Q1B further pushes port 6 of transistor Q1A to thehigh impedance state. Further, port FANPWR, the source of power for, byway of example, the power supply circuit drives the gate of transistorQ3 to logic one.

In an embodiment, transistor Q3 can be a ZXMP3A17E6 transistor. Logicone at the gate of transistor Q3 pushes transistor Q3 to cut-off regionthus discharging power stored in L3 and C4 through port PWROUT1.

Logic one at port 1 of comparator VCMP reverse biases diode D1, therebypushing diode D1 into cut-off region. Further, port LIMPWR startscharging capacitor C1. In an embodiment of the present invention,capacitor C1 can be a 100 picofarad (pf) capacitor. The time taken bythe capacitor C1 to charge to a threshold voltage is equal to the filteroff-time, in conjunction with FIG. 3. The threshold voltage is thevoltage that pushes transistor Q1B into an active region. The delay ofcapacitor C1 to reach the threshold voltage allows transistor Q3 tooperate in a completely on or a completely off state. Further, the delayof capacitor C1 is introduced to allow inductor L3 to discharge power.Transistor Q1B produces logic zero at port 4 of transistor Q1B. Logiczero at port 4 of transistor Q1B allows the control of transistor Q1A byFANPWM1. In an embodiment of the present invention, logic one at FANPWM1drives transistor Q1B into an active region. Transistor Q1B furtherpushes port 6 of transistor Q1A to logic zero. Logic zero at port 6 oftransistor Q1A drives transistor Q3 into an active region. Therefore,port PWROUT1 is driven by port FANPWR. Further, logic zero at portFANPWM1 drives transistor Q1A into a cut-off region. Cut-off oftransistor Q1A drives transistor Q3 into cut-off mode, discharging powerstored in L3 and C4 through PWROUT1.

In an embodiment of the invention, current sensing circuit 102 comprisesport GNDOUT1, resistor R3, and resistor R2; over-current comparatorcircuit 104 comprises comparator VCMP; low pas filter 106 comprisesresistor R1, capacitor C1, Diode D1; and one bit multiplier 108comprises transistor Q1B, and transistor Q1A.

In an embodiment of the present invention, capacitors C4, C3, and C2 areused as by-pass capacitors. Diode D2 is used as the catch diode for theswitching power supply formed by Q3, L3, C4, and D2.

As presented herein, the aspects of control of a PWM fan based on loadcurrent is independent of the master PWM signal. This independentoperation allows current limiting even when the master PWM signal isoperating in an open loop configuration or is controlled by factorsother than load current. Moreover, the present invention regulatescurrent with response time of the over-current comparator circuit incomparison to the slow response of fuses and circuit breakers. Thisinstantaneous response also serves to limit inrush current on startup.Further, the present invention allows load transient without userintervention. The system returns to normal operation when the loadcurrent returns to normal condition. Moreover, the low-pass filterfilters out the high-frequency component in the detected output makingthe detected output compatible with electromagnetic interferencereduction circuits.

The present invention also protects a software controlled system in theevent of failed software and recovers immediately when software isrestored.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A system for current limiting using a Pulse Width Modulation (PWM)control, the system comprising: a. a current sensing circuit for sensinga load current, the current sensing circuit produces a control voltageproportional to the load current; b. an over-current comparator circuitfor comparing the control voltage with a reference voltage, theover-current comparator circuit produces a detected output; c. alow-pass filter for delaying the detected output; and d. a multiplierfor multiplying the delayed detected output with a master PWM signal. 2.The system according to claim 1, wherein the system is used for a directcurrent motor.
 3. The system according to claim 1, wherein the detectedoutput and the master PWM signal operate independent of each other. 4.The system according to claim 1, wherein the detected output and themaster PWM signal have different frequencies.
 5. The system according toclaim 1, wherein the detected output and the master PWM signal have samefrequencies.
 6. The system according to claim 1, wherein the referencevoltage is proportional to a maximum current limit.
 7. The systemaccording to claim 1, wherein the current sensing circuit comprises aresistor to generate the control voltage proportional to the loadcurrent.
 8. The system according to claim 1, wherein the multiplier is aone-bit multiplier.
 9. The system according to claim 1, wherein thedetected output is logic zero if the load voltage is greater than thereference voltage, indicating an over-current condition.
 10. A methodfor current limiting using Pulse Width Modulation (PWM) control, themethod comprising: a. sensing a load current, wherein a control voltageis produced proportional to the load current; b. comparing the controlvoltage with a reference voltage, wherein the comparing produces adetected output; c. delaying the detected output; and d. multiplying thedelayed detected output with a master PWM signal.
 11. The methodaccording to claim 10, wherein the detected output and the master PWMsignal operate independent of each other.
 12. The method according toclaim 10, wherein the detected output and the master PWM signal havedifferent frequencies.
 13. The method according to claim 10, wherein thedetected output and the master PWM signal have same frequencies.
 14. Themethod according to claim 10, wherein the reference voltage isproportional to a maximum current limit.
 15. The method according toclaim 10, wherein the multiplying comprises bit-by-bit multiplication ofthe delayed detected output with the master PWM signal.
 16. The methodaccording to claim 10, wherein the delaying the detected outputcomprises extending off-cycle of the detected output.
 17. The methodaccording to claim 10, wherein the detected output is logic zero if theload voltage is greater than the reference voltage, indicating anover-current condition.